circuit GCD :
  module GCD :
    input clock : Clock
    input reset : UInt<1>
    input io_a : UInt<16>
    input io_b : UInt<16>
    input io_load : UInt<1>
    output io_out : UInt<16>
    output io_valid : UInt<1>

    reg x : UInt<16>, clock with :
      reset => (UInt<1>("h0"), x) @[gcd.scala 13:16]
    reg y : UInt<16>, clock with :
      reset => (UInt<1>("h0"), y) @[gcd.scala 14:16]
    node _T = gt(x, y) @[gcd.scala 18:15]
    node _T_1 = sub(x, y) @[gcd.scala 19:18]
    node _T_2 = tail(_T_1, 1) @[gcd.scala 19:18]
    node _T_3 = leq(x, y) @[gcd.scala 20:21]
    node _T_4 = sub(y, x) @[gcd.scala 21:18]
    node _T_5 = tail(_T_4, 1) @[gcd.scala 21:18]
    node _GEN_0 = mux(_T_3, _T_5, y) @[gcd.scala 20:25 gcd.scala 21:14 gcd.scala 14:16]
    node _GEN_1 = mux(_T, _T_2, x) @[gcd.scala 18:18 gcd.scala 19:14 gcd.scala 13:16]
    node _GEN_2 = mux(_T, y, _GEN_0) @[gcd.scala 18:18 gcd.scala 14:16]
    node _GEN_3 = mux(io_load, io_a, _GEN_1) @[gcd.scala 15:18 gcd.scala 16:10]
    node _GEN_4 = mux(io_load, io_b, _GEN_2) @[gcd.scala 15:18 gcd.scala 16:21]
    node _T_6 = eq(y, UInt<1>("h0")) @[gcd.scala 26:21]
    io_out <= x @[gcd.scala 25:17]
    io_valid <= _T_6 @[gcd.scala 26:17]
    x <= _GEN_3
    y <= _GEN_4